1. Field of the Invention
The present invention relates to the configuration of a nonvolatile memory formed by using a semiconductor. In particular, the invention for a nonvolatile memory in which the channel length is 2 μm or less or even 0.5 μm or less.
2. Description of the Related Art
The IC memories that perform data storage and holding in computers are generally classified into the RAM and the ROM. Examples of the RAM (random access memory) are the DRAM (dynamic RAM) and the SRAM (static RAM). If the power is turned off, data stored in the DRAM or the SRAM are lost.
On the other hand, examples of the ROM (read-only memory) are the mask ROM and the PROM (programmable ROM). The mask ROM and the PROM have an advantage that even if the power is turned off, data stored there are not lost. The PROM is classified into the EPROM (erasable PROM) in which data erasure is performed by using ultraviolet light, the EEPROM (electrically erasable PROM) in which data erasure is performed electrically, the flash memory (flash EEPROM) in which data erasure is performed en bloc electrically, and other types.
To fully utilize their marked advantage of permanent data holding, studies and developments on nonvolatile memories have been made energetically. At present, the possibility of using nonvolatile memories instead of magnetic memories is being discussed.
As for such IC memories, it is necessary to not only improve the reliability and performance but also increase the storage capacity. That is, as in the case of other types of ICs, such memory ICs are being developed according to the scaling law while miniaturization techniques are always adopted.
However, since basically nonvolatile memories store data according to the same principle of operation as field-effect transistors (hereinafter referred to as FETs), the short channel effect, which is known as causing serious problems in the FET operation, also causes serious problems in the operation of nonvolatile memories as the miniaturization advances.
In particular, the phenomenon called “punch-through” decreases the source-drain breakdown voltage and hence makes the current control with the gate electrode difficult. A SSW-DSA structure (Nikkei Microdevices, pp. 47-48, May issue, 1992) is a conventional example of increasing the punch-through resistance.
In the field of the FET, the SSW-DSA structure is a structure that utilizes a technique called a pocket structure in which an impurity region having the same conductivity type as the substrate is provided in the channel-drain junction portion. This structure can prevent the occurrence of a punch-through phenomenon by suppressing the expansion of the drain depletion layer.
However, in nonvolatile memories, electron-hole pairs are generated by positively causing impact ionization in the channel-drain junction portion. Therefore, a large amount of holes flow to the substrate side as electrons are injected into the floating gate.
However, in the SSW-DSA structure, a large amount of holes thus generated act in no other way than flow into the substrate terminal. This may cause a problem that a parasitic source-substrate-drain bipolar is formed to cause a kink phenomenon (an abnormal increase in drain current).